1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a method and apparatus for testing semiconductor devices at their operating speed.
2. Description of the Related Technology
Semiconductor integrated circuits are produced by manufacturing a wafer (a disk of silicon) having many copies, each copy called a "die" (plural "dice"), of the integrated circuit. Typically, not all the dice of a wafer work properly. Thus, the first thing that must be done after the wafer is processed is to determine which dice are good. Each die on the wafer must be tested to determine whether it functions correctly. This testing activity is called "wafer sort". Only the dice that pass wafer sort testing are packaged.
During testing, parameters such as propagation delay and drive currents are checked, a process called "parametric testing". Whether or not the die carries out the function it was designed for is also checked by a process called "functional testing". The cost of doing functional testing is increasing rapidly. This is due to the fact that the ratio between the number of semiconductor devices on a die to the number of connection pads or I/O pins is rising. In fact, functional testing may be the most expensive part of manufacturing an integrated circuit.
Automatic test equipment that functionally tests semiconductor dice has become very expensive. In addition, the computing time required to calculate input test patterns to be applied to the die during these tests is extremely costly. What the integrated circuit manufacturers have done to reduce functional testing costs is to include circuitry on each semiconductor die to facilitate testing thereof.
There are two types of functional tests that are utilized in computer systems. The first is "implicit" or concurrent testing or "checking". This test refers to on-line testing to detect errors that occur during normal system operation. The second is "explicit" testing. Explicit testing is carried out while the tested circuit (die) is not in use. Explicit testing includes the tests performed on dice while still on a wafer, production tests on packaged dice on boards, acceptance tests, maintenance tests, and repair tests.
In order to make testing of a resulting product economical, the semiconductor die must have a "design for testability (DFT)". DFT is utilized to increase the observability or controllability of a circuit design on a semiconductor die. The most direct way to do this is to introduce test points, i.e., additional circuit inputs and outputs to be utilized during testing. There is a cost, however, associated with adding test points. This cost may be justified, but the cost of test points soon becomes prohibitive because of the limited number of integrated circuit package pins available.
DFT requires additional logic and extra connections to the die, and it is desirable to limit these additions to those absolutely necessary to assure adequate testability of the design. The integrated circuit manufacturers have utilized various methods of estimating a design's testability. A straight forward method for determining the testability of a circuit is to use an Automatic Test Pattern Generation ("ATPG") program to generate the tests and the fault coverage. The running time of the program, the number of test patterns generated, and the fault coverage then provides a measure of the testability of the circuit.
In order to permit access to internal nodes of a circuit without requiring a separate external connection for each node requiring access, additional internal logic circuitry may be utilized primarily for the testing function. Using this test logic, it is possible to introduce scan-path test methods. Scan-path design is a DFT circuit design technique that partitions the circuit, as well as increases the observability and controllability of internal circuit nodes. Scan path design is suitable for synchronous, sequential circuits.
With scan-path design, testing of the semiconductor die is simpler and yet results in effective fault testing coverage. The scan-path technique requires that a circuit under test have two modes of operation: a normal functional mode and a test mode. The change from one mode to the other is controlled by a mode-select signal and/or by a separate test clock signal.
In the test mode, the scan elements shift data along the scan chain (as in a shift register). Thus, a test pattern can be scanned (shifted) into the scan chain, filling all scan elements with data. When the circuit under test returns to its normal functional mode, a system clock causes the test pattern to be stored in the system flip-flops and applied at the primary circuit inputs to be processed by the combinational logic part of the circuitry.
The results of the processing are stored back to the system flip-flops by the single system clock pulse. When the circuit is next placed into test mode, the resulting pattern, stored in the shift register, is then shifted out for comparison with the expected response. The ATPG program models of the scan flip-flops and latches aid the semiconductor die test designer in creating and verifying the resulting test patterns shifted out with the expected response generated from the ATPG program. A more detailed introduction to scan-path design techniques is given in Logic Design Principles, by Edward J. McCluskey, Prentice-Hall, 1986, and is incorporated by reference herein for all purposes.
Another important test is delay fault. The delay fault test uses the scan test to test for high speed faults. It is important in high speed semiconductor devices that not only do the circuits therein properly perform the required logic functions, but also that these circuits perform these logic functions correctly at the required speed. The combination of these tests may be called delayed ATPG.
A typical delayed ATPG test has four cycles in sequence as follows: a) scan in/out, b) strobe output, c) stabilize, and d) input. The scan in/out cycle is where data is scanned into and out of the scan chain of the semiconductor devices under test. The strobe output cycle is where the test data is strobed out of the scan chain in preparation for testing of the devices. The stabilize cycle is where the strobed data stabilizes in the semiconductor device circuits so as to avoid race conditions and internal bus conflicts before the input cycle. The input or capture cycle is where the strobed and stabilized data is transferred through the semiconductor device circuit logic by a system clock pulse at the desired operating speed of the logic devices.
After the input cycle, the next scan in/out cycle begins. The previous test results are shifted out while a new test pattern is shifted in. A comparison of the test results is made against an expected pattern and if there is a match, then the device has passed this part of the test. In the scan in/out cycle, data may be shifted into and out of the semiconductor device under test at a relatively slow speed such as, for example, 10 MHz. 10 MHz is high enough in frequency to allow shifting of the data test patterns into and out of the circuit devices without undue delay, but not so fast as to prevent standard digital logic test circuits from easily handling the data transfers. A more detailed description of this test methodology is detailed in Chip-Level Full Scan Design Methodology Guide, LSI Logic Corporation, January 1992, and incorporated herein by reference for all purposes.
Circuit devices of present technology semiconductor integrated circuit dice may operate at upwards of 200 MHz, and the promise of even faster devices is not too far in the future. 200 MHz devices must be tested in some fashion at their intended operating speed for the test to be meaningful. Therefore, at 200 MHZ operating speed, the input cycle must use a system clock having a 5 nanoseconds pulse width. The 5 nanosecond clock pulse causes the test pattern already scanned into the devices under test to propagate therethrough. The data pattern propagates through the test device logic and is held in the output scan register until the next scan in/out cycle. During the next scan in/out cycle, this pattern will be shifted out and compared to verify proper circuit operation.
A single system clock pulse, however, only "bangs" the previously setup data through the test device logic circuits, and the result of whatever propagates through is shifted out during the next scan in/out cycle. The aforementioned test only checks combinational logic function and does not test if the logical operations propagate through the logic being tested within a desired time period. Thus, logic operation may be correct but the time in which the logic circuits under test perform the logic operation is still unverified.
Attempts have been made to verify correct propagation time of logic devices by correlation. Correlation is when at least one path of a semiconductor device is clocked at operating speed, and correct operation of this path is verified. Thus, the device is correlated to function at a desired test speed.
What is needed is a method and apparatus which tests semiconductor devices at their operating speed. It is, therefore, an object of the present invention to test semiconductor devices at a desired operating speed with standard integrated circuit testers.